1. Field of the Invention
The present invention relates to semiconductor storage devices and more particularly to techniques of reducing noise in high-speed wide-bit output memories.
2. Description of the Related Art
As the performance of microprocessors including RISC's advances, there is a growing need for high-speed wide-bit output standard memories mainly used as cache memories. In wide-bit memories of, for example, .times.8 output or .times.16 output, on the other hand, output circuits are driven simultaneously when reading data and consequently large noise voltages are generated on internal power supply and ground lines, leading to erroneous operations of memory cells and internal circuits. Since the magnitude of noise voltage is proportional to a rate of change of current di/dt of the output circuit, compatibility of high speed with low noise is, in general, difficult to maintain. This problem is one of the most difficult technical problems encountered in development of high speed semiconductor memories. The problem has gradually been solved by improved circuit techniques and packaging techniques but such previous solutions seem to face a limit. For example, it is almost impossible for the present-day technique to realize a high-speed standard SRAM of .times.16 output having access time equivalent to that of a high-speed standard SRAM of .times.8 output.
JP-A-59-70314 discloses a technique of reducing noise due to simultaneous driving by making drive times of a plurality of output circuits different. This technique can advantageously achieve effective noise reduction but, disadvantageously, it increases delay time.
JP-A-59-181828 discloses a technique of reducing noise due to simultaneous driving by presetting output circuits to an intermediate potential between the power supply potential and a ground potential in advance. This technique, however, raises a problem that when the output is at the intermediate level, a circuit receiving the output is so affected by noise as to be liable to operate erroneously.
JP-A-63-24721 discloses a technique of reducing noise due to simultaneous driving by controlling rise time and fall time of the output circuit. In this technique, because of controlling of the rise time and fall time, delay time is disadvantageously increased.
As described above, the prior arts art devices fail to establish compatibility between reduction of noise due to simultaneous driving and high-speed operation.